The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique which is effective when applied to a semiconductor integrated circuit device comprising a static random access memory (hereinbelow, abbreviated to `SRAM`).
The memory cell of an SRAM is constructed of a flip-flop circuit wherein a pair of inverter circuits are cross-coupled. Each of the inverter circuits is arranged such that a load element and a drive MISFET (gate-insulated field effect transistor) are connected in series. The power source potential is applied to the common terminal of the two load elements thereto. The common source of the two drive MISFETs is supplied with the ground potential of circuitry.
A memory cell of the type in which a resistance element made of polycrystalline silicon is employed as a load element, has been known. The memory cell of this type is suited to high density integration because the resistance element can be formed over a drive MISFET. An SRAM having memory cells of this type has been disclosed in Japanese Patent Application Laid-open No. 54-128295 Japanese Patent Application No. 57-160999 or Japanese Patent Application No. 59-125247. It was also published as "A 30 ns 64k CMOS RAM" by Kim Hardee, Michael Griffus and Ron Galvas in IEEE International Solid-State Circuits Conference in 1984.